1. Field of the Invention
The present invention is concerned with anti-reflective coatings including polymers comprising unreacted ring members, and methods of using those coatings with low dielectric constant materials to inhibit or avoid via or photoresist poisoning normally associated with those materials.
2. Description of the Prior Art
The integrated circuit industry is continually moving towards denser device integration and faster device switching speeds. Through advanced semi-conductor processing techniques, integrated circuit devices with submicron feature sizes (i.e., less than 0.35 μm) can now be manufactured. This trend towards reduced feature size has, in turn, driven the need for multilayer interconnects.
The dual damascene process is a multi-level interconnection process in which, in addition to forming the grooves of the single damascene process, conductive contact or via holes are formed as well. In this scheme, circuit performance increasingly becomes a function of delay time of electronic signals traveling between the millions of gates and transistors present on an integrated circuit chip. Until recently, the integrated circuit R-C delay that determines device switching speeds was dominated by the CMOS transistor drive capacitance and load resistance. For submicron devices, the increase in signal delay due to capacitance of multilayer devices has become a limitation to improving device performance. To meet the speed and decreased crosstalk requirements for multilayer interconnect devices, it is desirable to use insulating materials having low dielectric constants (i.e., less than about 3.8) between metal interconnect lines. Some materials which have dielectric constants lower than 3.8 are disclosed in U.S. Pat. No. 6,054,380, incorporated by reference herein.
While use of these dielectric materials has been considered, they have not yet been incorporated into integrating circuit production lines. One of the primary technical difficulties preventing the use of these materials is a problem known as via poisoning or photoresist poisoning (see e.g., U.S. Pat. No. 6,103,456, incorporated by reference herein). A typical dual damascene process involves optical lithography techniques. In processes using a low dielectric constant material, the process would involve successively applying a barrier layer, a low dielectric constant layer, a hard mask layer, and an anti-reflective layer on a semiconductor substrate. Thereafter, the anti-reflective layer and low dielectric constant layer (also referred to as the low k dielectric layer) are patterned by photolithography with a photoresist layer to create openings or trenches. However, via or photoresist poisoning which occurs as a result of the low k dielectric material lying beneath the organic anti-reflective material has hindered the removal of the photoresist from the openings in the anti-reflective material. As this opening is critical to the subsequent steps of forming multilayer interconnects, the inability to clear the photoresist interferes with quality device fabrication.